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1 ? fn8106.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x28c512, x28c513 5v, byte alterable eeprom the x28c512, x28c 513 are 64k x 8 eeprom, fabricated with intersil?s proprietary, high performance, floating gate cmos technology. like all intersil programmable nonvolatile memories, the x28c512, x28c513 are 5v only devices. the x28c512, x28c513 feature t he jedec approved pin out for byte wide memories, compatible with industry standard eproms. the x28c512, x28c513 support a 128-byte page write operation, effectively providi ng a 39s/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. the x28c512, x28c513 also feature data polling and toggle bit polling, system software support schemes used to indicate the early co mpletion of a write cycle. in addition, the x28c512, x28c513 support the software data protection option. features ? access time: 90ns ? simple byte and page write - single 5v supply ? no external high voltages or v pp control circuits - self-timed ? no erase before write ? no complex programming algorithms ? no overerase problem ? low power cmos - active: 50ma - standby: 500a ? software data protection - protects data against system level inadvertent writes ? high speed page write capability ? highly reliable direct write ? cell - endurance: 100,000 write cycles - data retention: 100 years - early end of write detection -data polling - toggle bit polling ? two plcc and lcc pinouts - x28c512 ? x28c010 eprom pin compatible - x28c513 ? compatible with lower density eeproms ? pb-free plus anneal available (rohs compliant) data sheet june 7, 2006
2 fn8106.2 june 7, 2006 block diagram x buffers latches and decoder i/o buffers and latches y buffers latches and decoder control logic and timing 512kbit eeprom array i/o 0 -i/o 7 data inputs/outputs ce oe v cc v ss a 7 -a 15 we a 0 -a 6 ordering information part number part marking access time (ns) temp range (c) package x28c512d x28c512d - 0 to +70 32 ld cerdip x28c512dm x28c512dm -55 to +125 32 ld cerdip x28c512j x28c512j 0 to +70 32 ld plcc x28c513em x28c513em -55 to +125 32 ld lcc x28c512d-12 x28c512d-12 120 0 to +70 32 ld cerdip x28c512di-12 x28c512di-12 -40 to +85 32 ld cerdip x28c512dmb-12 x28c512dmb-12 mil-std-883 32 ld cerdip x28c512fmb-12 x28c512fmb-12 mil-std-883 32 ld flat pack x28c512j-12* x28c512j-12 0 to +70 32 ld plcc x28c512jz-12* (see note) x28c512j-12 z 0 to +70 32 ld plcc (pb-free) x28c512ji-12 x28c512ji-12 -40 to +85 32 ld plcc x28c512jiz-12* (see note) x28c512ji-12 z -40 to +85 32 ld plcc (pb-free) x28c512jm-12 x28c512jm-12 -55 to +125 32 ld plcc x28c512km-12 x28c512km-12 -55 to +125 36 ld cpga x28c512pi-12 x28c512pi-12 -40 to +85 32 ld pdip x28c512rmb-12 x28c512rmb-12 mil-std-883 32 ld flat pack x28c513em-12 x28c513em-12 -55 to +125 32 ld lcc x28c513emb-12 x28c513emb-12 mil-std-883 32 ld lcc x28c513j-12* x28c513j-12 0 to +70 32 ld plcc x28c513jz-12* (note) x28c513j-12 z 0 to +70 32 ld plcc (pb-free) x28c513ji-12* x28c513ji-12 -40 to +85 32 ld plcc x28c513jiz-12* (note) x28c513ji-12 z -40 to +85 32 ld plcc (pb-free) x28c513jm-12 x28c513jm-12 -55 to +125 32 ld plcc x28c512, x28c513
3 fn8106.2 june 7, 2006 x28c512d-15 x28c512d-15 150 0 to +70 32 ld cerdip x28c512di-15 x28c512di-15 -40 to +85 32 ld cerdip x28c512dmb-15 x28c512dmb-15 mil-std-883 32 ld cerdip x28c512j-15* x28c512j-15 0 to +70 32 ld plcc x28c512jz-15* (see note) x28c512j-15 z 0 to +70 32 ld plcc (pb-free) x28c512ji-15* x28c512ji-15 -40 to +85 32 ld plcc x28c512jiz-15* (see note) x28c512ji-15 z -40 to +85 32 ld plcc (pb-free) x28c512jm-15 x28c512jm-15 -55 to +125 32 ld plcc x28c513em-15 x28c513em-15 -55 to +125 32 ld lcc x28c513emb-15 x28c513emb-15 mil-std-883 32 ld lcc x28c513j-15* x28c513j-15 0 to +70 32 ld plcc x28c513jz-15* (note) x28c513j-15 z 0 to +70 32 ld plcc (pb-free) x28c513ji-15 x28c513ji-15 -40 to +85 32 ld plcc x28c513jiz-15* (note) x28c513ji-15 z -40 to +85 32 ld plcc (pb-free) x28c513jm-15 x28c513jm-15 -55 to +125 32 ld plcc x28c512dmb-20 x28c512dmb-20 200 mil-std-883 32 ld cerdip x28c512jm-20 x28c512jm-20 -55 to +125 32 ld plcc x28c512ki-20 x28c512ki-20 -40 to +85 36 ld cpga x28c512km-20 x28c512km-20 -55 to +125 36 ld cpga x28c513ei-20 x28c513ei-20 -40 to +85 32 ld lcc x28c513em-20 x28c513em-20 -55 to +125 32 ld lcc x28c513emb-20 x28c513emb-20 mil-std-883 32 ld lcc x28c513j-20t1 x28c513j-20 0 to +70 32 ld plcc tape and reel x28c512em-25 x28c512em-25 250 -55 to +125 32 ld lcc x28c512jm-25 x28c512jm-25 -55 to +125 32 ld plcc x28c512km-25 x28c512km-25 -55 to +125 36 ld cpga x28c512kmb-25 x28c512kmb-25 mil-std-883 36 ld cpga x28c513em-25 x28c513em-25 -55 to +125 32 ld lcc x28c513emb-25 x28c513emb-25 mil-std-883 32 ld lcc *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products em ploy special pb-free material sets; mold ing compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb -free soldering operations. intersil pb-free products are msl clas sified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking access time (ns) temp range (c) package x28c512, x28c513
4 fn8106.2 june 7, 2006 pinouts pin descriptions addresses (a 0 -a 15 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/write operations. when ce is high, power consumption is reduced. output enable (oe ) the output enable input contro ls the data output buffers and is used to initiate read operations. data in/data out (i/o 0 -i/o 7 ) data is written to or read from the x28c512, x28c513 through the i/o pins. write enable (we ) the write enable input controls the writing of data to the x28c512, x28c513. nc nc a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we nc a 14 a 13 a 8 a 9 a 11 oe a 10 ce i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 x28c512 plastic dip cerdip flat pack soic (r) bottom 14 a 0 16 i/o 1 18 v ss 11 a 3 9 a 5 7 a 7 15 i/o 0 17 i/o 2 19 i/o 3 5 a 15 2 nc 36 v cc 20 i/o 4 21 i/o 5 34 nc 23 i/o 7 25 a 10 27 a 11 29 a 8 22 i/o 6 32 nc 24 ce 26 oe 28 a 9 30 a 13 13 a 1 12 a 2 10 a 4 8 a 6 4 nc 3 nc 1 nc 35 we 33 nc 31 a 14 6 a 12 pga x28c512 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 a 14 i/o 1 a 12 a 15 nc nc v cc we nc 2 32 6 1 5 4 3 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 14 21 30 plcc/lcc i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 x28c513 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 9 a 11 nc oe a 10 ce i/o 6 a 8 i/o 1 a 7 a 12 v cc we 2 32 6 1 5 4 3 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 14 21 30 i/o 2 v ss nc i/o 3 i/o 4 i/o 5 a 14 a 15 a 13 i/o 7 view (top view) (top view) pin names symbol description a 0 -a 15 address inputs i/o 0 -i/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect x28c512, x28c513
5 fn8106.2 june 7, 2006 device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control ar chitecture eliminates bus contention in a system environ ment. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28c512, x28c513 support both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs first. a byte write operation, once initiated, will automatically continue to completion, typically within 5ms. page write operation the page write feature of th e x28c512, x28c513 allows the entire memory to be written in 2.5 seconds. page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the x28c512, x28c513, prior to the commencement of the internal programming cycle. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 7 through a 15 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following th e initial byte writ e cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. each successive byte load c ycle, started by the we high to low transition, must begin within 100s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100s, the internal automatic programming cycle will commence. there is no page write window limitation. effectively, the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. write operation status bits the x28c512, x28c513 provide the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. data polling (i/o 7 ) the x28c512, x28c513 feature data polling as a method to indicate to the host system that the byte write or page write cycle has completed. data polling allows a simple bit test operation to determine the status of the x28c512, x28c513, eliminating additional interrupt inputs or external hardware. during the inte rnal programming cycle, any attempt to read the last byte written will produce the complement of that data on i/o 7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will reflect true data. toggle bit (i/o 6 ) the x28c512, x28c513 also provide another method for determining when the internal write cycle is complete. during the internal progr amming cycle, i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device. when the internal cycle is complete, the toggling will cease, and the device will be accessible for additional read or write operations. 5 tb dp 43210 i/o reserved toggle bit data polling figure 1. status bit assignment x28c512, x28c513
6 fn8106.2 june 7, 2006 data polling i/o 7 data polling can effectively halve the time for writing to the x28c512, x28c513. the timing diagram in figure 2a illustrates the sequence of events on the bus. the software flow diagram in figure 2b illustrates one method of implementing the routine. ce oe we i/o 7 x28c512, x28c513 ready last write high z v ol v ih a 0 -a 15 a n a n a n a n a n a n v oh a n figure 2a. data polling bus sequence write data save last data and address read last address io 7 compare? ready no yes writes complete? no yes figure 2b. data polling software flow x28c512, x28c513
7 fn8106.2 june 7, 2006 the toggle bit i/o 6 the toggle bit can eliminate the chore of saving and fetching the last address and data in order to implement data polling. this can be especially helpful in an array comprised of multiple x28c512, x28c513 memories that are frequently updated. toggle bit polling can also provide a method for status checking in multiprocessor applications. the timing diagram in figure 3a illustrates the sequence of events on the bus. the software flow diagram in figure 3b illustrates a method for polling the toggle bit. hardware data protection the x28c512, x28c513 provide three hardware features that protect nonvolatile dat a from inadvertent writes. - noise protection?a we pulse typically less than 10ns will not initiate a write cycle. - default v cc sense?all write functions are inhibited when v cc is 3.6v. - write inhibit?holding either oe low, we high, or ce high will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. write cycle timing specific ations must be observed concurrently. software data protection the x28c512, x28c513 offer a software controlled data protection feature. the x28c512, x28c513 are shipped from intersil with the soft ware data protection not enabled; that is, the device will be in the standard operating mode. in this mo de data should be protected during power-up/-down operat ions through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. the x28c512, x28c513 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. the internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the x28c512, x28c513 are also protected from inadvertent and accidental writes in the powered-up stat e. that is, the software algorithm must be issued prior to writing additional data to the device. note: the data in the three-byte enable sequence is not written to the memory array. ce oe we x28c512, x28c513 last write i/o 6 high z * * v oh v ol ready * beginning and ending state of i/o 6 will vary. figure 3a. toggle bit bus sequence compare x28c512 no yes ok? compare accum with addr n load accum from addr n last write ready figure 3b. toggle bit software flow x28c512, x28c513
8 fn8106.2 june 7, 2006 software data protection software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. refer to figures 4a and 4b for the sequence. the three byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. once the page load cycle has been completed, the device will automatically be returned to the data protected state. regardless of whether the device has previously been protected or not, once the soft ware data protected algorithm is used and data has been wr itten, the x28c512, x28c513 will automatically disable furt her writes, unless another command is issued to cancel it. if no further commands are issued the x28c512, x28c513 wi ll be write-protected during power-down and after any subsequent power-up. the state of a 15 while executing the algorithm is ?don?t care?. note: once initiated, the sequence of write operations should not be interrupted. ce we (v cc ) write protected v cc 0v data addr aaa 5555 55 2aaa a0 5555 t blc max writes ok byte or page t wc note: all other timings and control pins are per page write timing requirements figure 4a. timing sequence?software data protect enable sequence followed by byte or page write write last write data xx to any write data 80 to address 5555 write data 55 to address 2aaa write data aa to address 5555 after t wc re-enters data protected state byte to last address address optional byte/page load operation figure 4b. write sequence for software data protection x28c512, x28c513
9 fn8106.2 june 7, 2006 resetting software data protection in the event the user wants to deactivate the software data protection feature for test ing or reprogramming in an eeprom programmer, the following six step algorithm will reset the internal protec tion circuit. after t wc , the x28c512, x28c513 will be in standard operating mode. note: once initiated, the sequence of write operations should not be interrupted. system considerations because the x28c512, x28c513 are frequently used in large memory arrays, it is provided with a two-line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipation and eliminate the possibility of cont ention where multiple i/o pins share the same bus. to gain the most benefit, it is recommended that ce be decoded from the address bus and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation this assures that all deselected devices are in their standby mode and that only the select ed device(s) is/are outputting data on the bus. because the x28c512, x28c513 have two power modes, (standby and active), proper decoupling of the memory array is of prime concern. enabling ce will cause transient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of th e i/os. therefor e, the larger the array sharing a common bu s, the larger the transient spikes. the voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capaci tors. as a minimum, it is recommended that a 0.1f high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended th at a 4.7f electrolytic bulk capacitor be placed between v cc and v ss for each 8 devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces. ce we standard operating mode v cc data addr aaa 5555 55 2aaa 80 5555 t wc aa 5555 55 2aaa 20 5555 note: all other timings and control pins are per page write timing requirements figure 5a. reset software data protection timing sequence write data 55 to address 2aaa write data 55 to address 2aaa write data a0 to address 5555 write data aa to address 5555 write data 20 to address 5555 write data aa to address 5555 figure 5b. software sequence to deactivate software data protection x28c512, x28c513
10 fn8106.2 june 7, 2006 active supply current vs ambient temperature standby supply current vs ambient temperature i cc (rd) by temperature over frequency -55 -10 +125 10 11 12 13 14 ambient temperature (c) 8 +35 +80 v cc = 5v 9 i cc (ma) -55 -10 +125 0.14 0.16 0.18 0.2 0.24 ambient temperature (c) 0.1 +35 +80 0.22 v cc = 5v 0.12 i sb (ma) 0 315 30 40 50 60 5.0 v cc frequency (mhz) 10 69 -55c +25c +125c 12 20 70 i cc (ma) x28c512, x28c513
11 fn8106.2 june 7, 2006 note: 2. this parameter is periodically sampled and not 100% tested. absolute maximum ratings recommended operating conditions temperature under bias x28c512, x28c513 . . . . . . . . . . . . . . . . . . . . . . . .-10c to +85c x28c512i/513i . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +135c x28c512m/513m . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . . . -1v to +7v d.c. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300c temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c supply voltage limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 10% caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. dc electrical specifications over recommended operating conditions , unless otherwise specified. symbol parameter test conditions min max unit i cc v cc current (active) (ttl inputs) ce = oe = v il , we = v ih , all i/o?s = open, address inputs = 0.4v/2.4v levels @ f = 5mhz 50 ma i sb1 v cc current (standby) (ttl inputs) ce = v ih , oe = vil, all i/o?s = open, other inputs = v ih 3ma i sb2 v cc current (standby) (cmos inputs) ce = v cc - 0.3v, oe = vil, all i/o?s = open, other inputs = v ih 500 a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc , ce = v ih 10 a v ll (note 1) input low voltage -1 0.8 v v ih (note 1) input high voltage 2v cc + 1 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = -400a 2.4 v note: 1. v il min. and v ih max. are for reference only and are not tested. power-up timing symbol parameter max unit t pur (note 2) power-up to read operation 100 s t puw (note 2) power-up to write operation 5 ms capacitance t a = +25c, f = 1mhz, v cc = 5v symbol parameter test conditions max unit c i/o (note 2) input/output capacitance v i/o = 0v 10 pf c in (note 2) input capacitance v in = 0v 10 pf endurance and data retention parameter min max unit endurance 10,000 cycles per byte endurance 100,000 cycles per page data retention 100 years x28c512, x28c513
12 fn8106.2 june 7, 2006 equivalent a.c. load circuit symbol table a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v mode selection ce oe we mode i/o power llh read d out active lhl write d in active hxx standby and write inhibit high z standby xlx write inhibit ? ? xxh write inhibit ? ? 5v 1.92k ? 100pf output 1.37k ? waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x28c512, x28c513
13 fn8106.2 june 7, 2006 read cycle note: 3. t lz min., t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. ac electrical specifications over the recommended operating condi tions, unless otherwise specified. symbol parameter x28c512-90 x28c512-12 x28c512-15 x28c512-20 x28c512-25 unit x28c513-90 x28c513-12 x28c513-15 x28c513-20 x28c513-25 min max min max min max min max min max read cycle limits t rc read cycle time 90 120 150 200 250 ns t ce chip enable access time 90 120 150 200 250 ns t aa address access time 90 120 150 200 250 ns t oe output enable access time 40 50 50 50 50 ns t lz (note 3) ce low to active output 0 0 0 0 0 ns t olz (note 3) oe low to active output 0 0 0 0 0 ns t hz (note 3) ce high to high z output 40 50 50 50 50 ns t ohz (note 3) oe high to high z output 40 50 50 50 50 ns t oh output hold from address change 0 0 0 0 0 ns t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid x28c512, x28c513
14 fn8106.2 june 7, 2006 we controlled write cycle note: 4. t wc is the minimum cycle time to be allowed from the system perspective unless po lling techniques are used. it is the maximum time the device requires to complete the internal write operation. write cycle limits symbol parameter min max unit t wc (note 4) write cycle time 10 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 100 ns t oes oe high setup time 10 ns t oeh oe high hold time 10 ns t wp we pulse width 100 ns t wph we high recovery 100 ns t dv data valid 1s t ds data setup 50 ns t dh data hold 0 ns t dw delay to next write 10 s t blc byte load cycle 0.2 100 s address t as t wc t ah t oes t dv t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp x28c512, x28c513
15 fn8106.2 june 7, 2006 ce controlled write cycle page write cycle notes: 5. between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. 6. the timings shown above are unique to page write operations. indi vidual byte load operations within the page write must confo rm to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t cs t dv t ds t dh t ch ce we oe data in data out high z data valid t cw t wph we oe last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address* i/o *for each successive write within the page write operation, a 7 -a 15 should be the same or writes to an unknown address could occur. (note 6) (note 5) x28c512, x28c513
16 fn8106.2 june 7, 2006 data polling timing diagram (note 7) toggle bit timing diagram note: 7. polling operations are by definit ion read cycles and are therefor e subject to read cycle timings. address a n d in = x t wc t oeh t oes ce we oe i/o 7 t dw a n a n d out = x d out = x ce oe we i/o 6 t oes t dw t wc t oeh high z * * *starting and ending state wi ll vary, depending upon actual t wc . x28c512, x28c513
17 fn8106.2 june 7, 2006 packaging information 0.620 (15.75) 0.590 (14.99) typ. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) typ. 0.100 (2.54) 1.690 (42.95) max. 0.023 (0.58) 0.014 (0.36) typ. 0.018 (0.46) 0.232 (5.90) max. 0.060 (1.52) 0.015 (0.38) pin 1 0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.033 (0.84) typ. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) max. 0 15 32-lead hermetic dual in-line package type d note: all dimensions in inches (in parentheses in millimeters) 0.005 (0.13) min. 0.150 (3.81) min. 0.015 (0.38) 0.008 (0.20) seating plane x28c512, x28c513
18 fn8106.2 june 7, 2006 packaging information 0.150 (3.81) bsc 0.458 (11.63) -- 0.458 (11.63) 0.442 (11.22) pin 1 0.020 (0.51) x 45 ref. 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) typ. (4) plcs. 0.040 (1.02) x 45 ref. typ. (3) plcs. 0.050 (1.27) bsc 0.028 (0.71) 0.022 (0.56) (32) plcs. 0.200 (5.08) bsc 0.558 (14.17) -- 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) pin 1 index corner 32-pad ceramic leadless chip carrier package type e note: 1. all dimensions in inch es (in parentheses in millimeters) 2. tolerance: 1% nlt 0.005 (0.127) 0.300 (7.62) bsc 0.015 (0.38) min. 0.400 (10.16) bsc 0.560 (14.22) 0.540 (13.71) dia. 0.015 (0.38) 0.003 (0.08) x28c512, x28c513
19 fn8106.2 june 7, 2006 packaging information 32-lead ceramic flat pack type f note: all dimensions in inches (in parentheses in millimeters) 0.019 (0.48) 0.015 (0.38) 0.045 (1.14) max. pin 1 index 132 0.120 (3.05) 0.090 (2.29) 0.026 (0.66) 0.007 (0.18) 0.004 (0.10) 0.370 (9.40) 0.270 (6.86) 0.830 (21.08) max. 0.050 (1.27) bsc 0.440 (11.18) 0.430 (10.93) 0.347 (8.82) 0.330 (8.38) 0.005 (0.13) min. 0.030 (0.76) min. 1.228 (31.19) 1.000 (25.40) min. x28c512, x28c513
20 fn8106.2 june 7, 2006 x28c512, x28c513 plastic leaded chip carrier packages (plcc) a1 a seating plane 0.015 (0.38) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 pin (1) c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.050 (1.27) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l ne nd identifier (0.12) m ds - b s as 0.042 (1.07) 0.048 (1.22) 0.005 n32.45x55 (jedec ms-016ae issue a) 32 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.125 0.140 3.18 3.55 - a1 0.060 0.095 1.53 2.41 - d 0.485 0.495 12.32 12.57 - d1 0.447 0.453 11.36 11.50 3 d2 0.188 0.223 4.78 5.66 4, 5 e 0.585 0.595 14.86 15.11 - e1 0.547 0.553 13.90 14.04 3 e2 0.238 0.273 6.05 6.93 4, 5 n28 286 nd 7 7 7 ne 9 9 7 rev. 0 7/98 notes: 1. controlling dimension: inch . converted millimeter dimen- sions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. al- lowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are mea- sured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. 7. nd denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. ne denotes the num- ber of leads on the two long sides of the package. -c-
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8106.2 june 7, 2006 x28c512, x28c513 ceramic pin grid array package (cpga) g36.760x760a 36 lead ceramic pin grid array package rev. 0 12/05 note: all dimensions in inches (in parentheses in millimeters). 15 17 19 21 22 14 16 18 20 23 10 9 27 28 8 7 29 30 5 2 36 34 32 4 3 1 35 33 typ. 0.100 (2.54) all leads pin 1 index note: leads 5, 14, 23, & 32 12 11 25 26 13 6 31 24 typ. 0.180 (.010) (4.57 .25) 4 corners 0.770 (19.56) 0.750 (19.05) sq a a 0.185 (4.70) 0.175 (4.45) 0.020 (0.51) 0.016 (0.41) 0.072 (1.83) 0.062 (1.57) 0.120 (3.05) 0.100 (2.54) typ. 0.180 (.010) (4.57 .25) 4 corners 0.050 (1.27) 0.008 (0.20) a a

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